Memory manufacturers may provide redundant memory structures on a memory module. When the memory is tested, after manufacture and prior to shipment, the redundant structures can be used to repair the memory cell array, allowing an otherwise defective part to be correct and used. This increases manufacture yield and decreases costs.
In a previous implementation of a memory cell array, an entire data byte, 8 bits, or word, 16 bits, was read out from a single column of physically adjacent bit cells. A single column consisted of n bitline pairs that would produce n data bits when accessed. Repair of defects in this type of array generally involved replacing a column having a defect with a spare column having the same number of bitline pairs as the column with the defect. All data bits in the column containing the defect were replaced in this scheme. A group of 32 spare bitlines, organized into 2 16-bit spare column elements, could be used to repair up to 2 column defects.
In newer memory implementations, each group of n bitlines produces a single data bit output, depending upon a column multiplexer ratio. For example, a group of 8 physically adjacent bitline pairs would produce one data bit, assuming the column multiplexer ratio was 8:1. The next set of 8 adjacent bitline pairs would produce the next data bit. Defects in memory arrays have a very random nature, and it would be desirable to provide each data bit with 2 possible repair elements, equivalent to the previous scheme. However in order to do so would require 256 spare bitline pairs, 8*16*2. This increases the array overhead 8 times for redundancy.